PCB Reverse Engineering Glossary: 40 Essential Terms Every Engineer Should Know
A PCB reverse engineering glossary is a reference of the specialized vocabulary used when an existing printed circuit board is analyzed, documented, and reconstructed into manufacturable design files. The definitions below cover the full workflow—from initial board inspection through delayering, schematic capture, and final verification—so engineers, procurement teams, and repair technicians can communicate with precision when scoping a reverse engineering project.
Why a Dedicated PCB Reverse Engineering Glossary Matters
Standard electronics dictionaries skip the operational terms that define day-to-day reverse engineering work. Words like “delayering,” “pad-stack extraction,” or “blind via identification” carry specific procedural meaning in a reverse engineering lab that differs from their textbook definitions. Misunderstanding even one term can lead to incorrect quoting, missed tolerances, or wasted board samples.
This glossary is written from our engineers’ bench notes—every definition reflects how the term is actually used during board recovery, not how it appears in a generic EDA manual. If you are evaluating a PCB copy and file-recovery service, these are the terms you will encounter in feasibility reports, deliverable lists, and technical discussions.
Core Process Terms (A–D)
| Term | Definition |
|---|---|
| Annular Ring | The copper pad area surrounding a drilled hole on a PCB. During reverse engineering, annular ring width (typically 0.05–0.25 mm) is measured to reconstruct accurate pad-stack geometry. |
| Back-Drilling | A manufacturing technique where unused via stubs are drilled out. Reverse engineers must identify back-drilled vias to avoid misinterpreting open connections on inner layers. |
| Bill of Materials (BOM) | A complete list of every component on the board—part numbers, values, packages, and quantities. BOM extraction is a standard deliverable in most reverse engineering projects. |
| Blind Via | A plated hole connecting an outer layer to one or more inner layers without passing through the entire board. Identifying blind vias requires cross-sectioning or X-ray imaging. |
| Board Outline | The mechanical boundary of the PCB, including cutouts, slots, and mounting holes. Captured as a DXF or Gerber mechanical layer, usually within ±0.05 mm tolerance. |
| Buried Via | A via connecting two or more inner layers with no exposure on either outer surface. These are invisible to optical scanning and require delayering or CT scanning to map. |
| Component Footprint | The land pattern (pads, silkscreen, courtyard) for a specific component. Footprint reconstruction is one of the most time-consuming steps, especially for proprietary or obsolete packages. |
| Cross-Section | A physical cut through the PCB stackup, polished and examined under a microscope to measure layer thicknesses, copper weights, and dielectric materials. Typical resolution: 1 µm. |
| Delayering | The controlled removal of PCB layers—chemically or mechanically—to expose and photograph each copper layer individually. This is the foundation of multi-layer board reverse engineering. A 12-layer board may require 20+ processing steps. |
| Design Rule Check (DRC) | An automated verification pass in EDA software that flags violations such as insufficient clearance, missing connections, or trace-width errors in the reconstructed design files. |
File Format and Output Terms (E–G)
| Term | Definition |
|---|---|
| EDA (Electronic Design Automation) | Software used to create, edit, and verify PCB layouts. Common platforms include Altium Designer, KiCad, Cadence Allegro, and PADS. Reverse-engineered data is typically delivered in the client’s preferred EDA format. |
| Excellon Drill File | A CNC-format file specifying drill hole locations, diameters, and types (plated/non-plated). Drill files are a mandatory output alongside Gerber data for fabrication. |
| Fiducial | A reference mark on the PCB surface used by pick-and-place machines for alignment. Fiducials are captured in the reverse-engineered paste and copper layers. |
| Gerber File | The industry-standard 2D image format (RS-274X / Gerber X2) describing each copper, solder mask, silkscreen, and paste layer. A complete reverse engineering deliverable includes one Gerber per layer plus drill files. |
| Golden Board | A known-good reference board used for comparison during reverse engineering. Having a functioning golden board accelerates netlist verification significantly. |
Understanding these output formats is critical when reviewing a breakdown of PCB reverse engineering costs, since deliverable complexity directly affects project pricing.
Inspection and Imaging Terms (H–N)
| Term | Definition |
|---|---|
| HDI (High-Density Interconnect) | A board class using microvias (≤0.15 mm), fine trace/space (≤75 µm), and sequential lamination. HDI boards are among the most challenging to reverse engineer due to stacked or staggered microvia structures. |
| Impedance Control | The design practice of maintaining specific trace impedance values (commonly 50 Ω single-ended, 90–100 Ω differential). Reverse engineers must measure stackup dimensions and dielectric constants to reconstruct impedance profiles. |
| IPC Class | Quality classification per IPC-6011/6012. Class 2 (dedicated service electronics) and Class 3 (high-reliability) define acceptance criteria for the reconstructed board. Most commercial reverse engineering targets Class 2. |
| Layer Stackup | The ordered arrangement of copper and dielectric layers in a multi-layer PCB—including copper weights (typically 0.5–2 oz), prepreg types, and core thicknesses. Stackup reconstruction is essential for impedance-controlled designs. |
| Microvia | A laser-drilled via with a diameter ≤150 µm, typically connecting adjacent layers. Microvias can be stacked, staggered, or filled—each configuration requires different identification techniques during delayering. |
| Netlist | A text-based list of every electrical connection (net) on the board, specifying which component pins connect to which. Netlist extraction is the bridge between physical board analysis and schematic capture. |
| Non-Destructive Testing (NDT) | Inspection methods—X-ray, CT scan, ultrasonic—that reveal internal features without damaging the board. NDT is used when only one sample board is available and cannot be sacrificed. |
For a walkthrough of how these inspection steps fit together, see our step-by-step PCB copy workflow page.
Reconstruction and Verification Terms (O–S)
| Term | Definition |
|---|---|
| ODB++ | A comprehensive PCB data format (developed by Valor/Siemens) that bundles copper layers, drill data, netlist, BOM, and component placement into a single database. Some clients prefer ODB++ over individual Gerbers. |
| Optical Scanning | High-resolution photography (typically 1200–4800 DPI) of each exposed copper layer. The resulting images are the raw input for digital tracing in EDA software. |
| Pad Stack | The complete set of pads and anti-pads for a single through-hole or via across all layers. Accurate pad-stack reconstruction ensures correct connectivity and manufacturability. |
| Pick-and-Place File | A coordinate file listing every component’s X/Y position, rotation, and reference designator. This file enables automated assembly of the reverse-engineered board. |
| Reverse Engineering | The systematic process of analyzing an existing physical PCB to extract its design data—schematic, layout, BOM, and firmware—so the board can be understood, modified, or re-manufactured. |
| Schematic Capture | The reconstruction of a circuit schematic from the extracted netlist and identified components. This is the most intellectually demanding phase, requiring an engineer who understands the circuit’s function. |
| Solder Mask | The protective coating (typically green, but available in many colors) applied over copper traces. Solder mask openings define solderable areas and are captured as a separate Gerber layer. |
| Stackup Analysis | The process of determining layer count, material types, copper weights, and dielectric thicknesses from a physical board—usually via cross-sectioning and measurement under a metallurgical microscope. |
Advanced and Security-Related Terms (T–Z)
| Term | Definition |
|---|---|
| Test Point | An exposed pad or via designated for electrical testing (ICT or flying probe). Reverse engineers document test points to maintain testability in the reconstructed design. |
| Thermal Relief | A pad connection pattern on power/ground planes that uses narrow spokes instead of a full connection, improving solderability. These are reconstructed per IPC-7351 guidelines. |
| Trace/Space | The width of a copper trace and the gap between adjacent traces, measured in mils or mm. Typical values range from 3/3 mil (76/76 µm) on HDI boards to 8/8 mil (200/200 µm) on standard 4-layer designs. |
| Via-in-Pad | A via placed directly in a component pad, typically filled and planarized. Common in BGA layouts. Reverse engineers must distinguish filled via-in-pad from standard through-hole vias to ensure correct fabrication notes. |
| X-Ray Inspection | 2D or 3D (CT) X-ray imaging used to see hidden features: BGA solder joints, inner-layer vias, embedded components. Resolution on modern systems reaches 1–5 µm. |
| Conformal Coating | A thin protective film (acrylic, silicone, urethane, or epoxy) applied over assembled boards. Must be carefully removed before component identification and delayering can begin. |
| Copper Pour / Plane | A large area of copper on a layer, typically used for power or ground distribution. Reverse engineers must capture pour boundaries, clearances, and thermal relief patterns accurately. |
| Counterfeit Detection | The process of identifying non-genuine components during BOM extraction. Decapsulation, marking analysis, and X-ray comparison against known-good parts are common techniques. |
| Potting Compound | An opaque encapsulant (epoxy or silicone) covering part or all of a board to obscure components. Removal without damaging the board requires chemical solvents or careful mechanical milling. |
| Board Protection | Any deliberate measure—potting, trace obfuscation, component sanding, tamper-evident seals—designed to make reverse engineering more difficult. Our guide on methods used to protect boards from reverse engineering covers twelve common techniques and their effectiveness. |
How These Terms Map to a Typical Project
A real reverse engineering project moves through these terms in roughly this order:
- Intake: Board outline measurement, conformal coating / potting compound removal, initial optical scanning and X-ray inspection.
- Analysis: Stackup analysis via cross-section, layer count confirmation, BOM extraction and counterfeit detection.
- Delayering: Chemical or mechanical delayering, high-resolution optical scanning of each copper layer, blind/buried/micro via identification.
- Reconstruction: Digital tracing in EDA software, pad-stack and component footprint reconstruction, netlist extraction, impedance control recalculation.
- Verification: DRC, netlist comparison against physical board, golden board functional test where available.
- Deliverables: Gerber files, Excellon drill files, pick-and-place file, BOM, schematic (if scoped), ODB++ package.
You can review the board sample condition and quantity checklist before sending a board for evaluation.
Quick-Reference: Abbreviations Used in Reverse Engineering Reports
| Abbreviation | Full Form | Context |
|---|---|---|
| BOM | Bill of Materials | Component list deliverable |
| DRC | Design Rule Check | File verification step |
| HDI | High-Density Interconnect | Board class with microvias |
| ICT | In-Circuit Test | Electrical test method |
| NDT | Non-Destructive Testing | X-ray / CT inspection |
| PTH | Plated Through-Hole | Via / component hole type |
| SMD / SMT | Surface-Mount Device / Technology | Component mounting style |
Frequently Asked Questions
What is the most misunderstood term in PCB reverse engineering?
Delayering is frequently confused with simple board disassembly. It actually refers to the controlled, layer-by-layer removal of copper and dielectric material—a destructive process that requires a sacrificial board sample. Non-destructive alternatives (CT scanning) exist but produce lower-resolution data, especially on boards with more than 8 layers.
How many Gerber files should a complete reverse engineering deliverable include?
At minimum, one Gerber per copper layer, plus solder mask top/bottom, silkscreen top/bottom, paste top/bottom, board outline, and one or more Excellon drill files. A 6-layer board typically yields 12–14 individual files. Add pick-and-place and BOM for assembly-ready packages.
What does “netlist extraction” involve, and why does it matter?
Netlist extraction maps every electrical connection between component pins by tracing copper paths across all layers. It is the step that converts a set of images into a verifiable electrical design. Without a correct netlist, the reconstructed board may look right but fail electrically. Our engineers cross-check the extracted netlist against physical continuity measurements.
Is there a difference between “PCB copy” and “PCB reverse engineering”?
PCB copy typically refers to reproducing an exact 1:1 clone of a board for re-manufacturing. PCB reverse engineering is broader—it can include schematic recovery, design modification, component substitution, or failure analysis. A copy project is a subset of reverse engineering. See our engineering team for project-specific clarification.
Do all reverse engineering labs use the same terminology?
No. Terms vary between regions and companies. For example, “board stripping” and “delayering” describe similar processes; “netlist extraction” may be called “connectivity mapping.” This glossary reflects the terminology our lab uses and that is most common in IPC and IEEE literature.
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