How Much Does Schematic Recovery Actually Cost?
Schematic recovery cost typically falls between $400 and $6,000 or more for a single board, depending on layer count, net count, component density, and whether firmware readout is required alongside the schematic. A straightforward 2-layer consumer board with 80–150 components usually sits at the low end, while a 10+ layer industrial control board with BGA packages and high-speed differential pairs can push well past $4,000. Our engineers price every project individually after evaluating the physical board or high-resolution scans, but the table below gives realistic starting ranges.
Schematic Recovery Pricing Table
| Board Complexity | Layer Count | Typical Net Count | Price Range (USD) | Lead Time (Working Days) |
|---|---|---|---|---|
| Simple consumer / IoT | 1–2 | 50–200 | $400 – $900 | 5–8 |
| Mid-range embedded | 4 | 200–600 | $900 – $2,200 | 8–12 |
| Complex industrial / telecom | 6–8 | 600–1,500 | $2,200 – $4,500 | 12–18 |
| High-density / HDI / server | 10–16+ | 1,500+ | $4,500 – $6,000+ | 18–30 |
These figures cover schematic-only recovery. If you also need Gerber files, the combined project cost is typically 15–25% less than ordering each deliverable separately — see our Gerber reverse engineering pricing guide for that breakdown.
What Drives Schematic Recovery Cost Up or Down?
Layer Count and Buried Vias
Every additional copper layer adds imaging, registration, and net-tracing work. Blind and buried vias on HDI boards are especially time-consuming because they can’t be optically traced from the surface alone. Our process uses controlled cross-sectioning and micro-CT where needed, and that equipment time is reflected in the quote. A 12-layer board with stacked microvias can take 3× the engineering hours of a 4-layer board with the same footprint.
Component Density and Package Types
A board carrying 600 passives in 0201 packages plus multiple 0.4 mm-pitch BGAs is harder to probe and map than a through-hole-dominant design with 150 parts. BGA pads hidden beneath the package require X-ray imaging to confirm connectivity, adding $150–$400 to the project depending on the number of BGA sites. QFN exposed pads and chip-scale packages present similar challenges.
Board Condition
Damaged, corroded, or partially delaminated boards increase risk and cost. If solder mask is burned away or copper has oxidized through, net continuity testing becomes unreliable and engineers must cross-reference multiple techniques. Boards with conformal coating need chemical or mechanical removal first — budget an extra $100–$300 and 1–2 days for that step.
Firmware or IC Readout Requirements
Some projects need more than a schematic. If the goal is full board replication, you may also need BOM extraction and firmware recovery. Bundling BOM extraction with schematic recovery typically adds $200–$600 depending on unique part count. IC readout costs vary widely by chip family and protection level.
Urgency
Our standard lead times are listed in the table above. Rush service (≤50% of standard lead time) carries a 30–50% surcharge. Extreme rush (3 working days for a 4-layer board, for example) may be possible but is quoted case-by-case after feasibility review.
What Do You Get? Deliverable Formats
A completed schematic recovery project from our lab delivers:
- Schematic files — Altium .SchDoc, KiCad .kicad_sch, OrCAD .dsn, or PDF, per your preference.
- Net list — exported in IPC-D-356 or your EDA tool’s native format for cross-checking against Gerber data.
- Component reference map — annotated board photo or overlay showing every designator and its physical location.
- Revision notes — any ambiguities, unresolvable nets, or assumptions documented explicitly so your engineering team can verify.
If the project scope includes Gerber and BOM, those are delivered in the same package with matched designators across all files.
How the Schematic Recovery Process Works
- Board intake and imaging — High-resolution optical scans of every layer (after controlled delamination on multi-layer boards), plus X-ray imaging of BGA and buried-via areas.
- Net extraction — Automated and manual tracing of every copper net from pad to pad, cross-referenced with continuity testing on the physical board.
- Component identification — Every part is cataloged by package, marking code, and value. Unmarked passives are measured in-circuit where possible.
- Schematic drafting — Nets and components are organized into logical functional blocks (power supply, MCU core, communication interfaces, analog front-end, etc.) following standard schematic conventions.
- Verification — The drafted schematic is back-annotated against the physical board. Net-by-net checks catch missed connections, especially on dense ground and power planes.
- Delivery and revision — Files are delivered for your review. One round of corrections based on your feedback is included in the quoted price.
End-to-end, a mid-complexity 4-layer board goes from intake to delivery in roughly 8–12 working days. Projects requiring full circuit board cloning — schematic, Gerber, BOM, and firmware — follow the same process but with parallel workstreams for each deliverable.
Common Mistakes That Inflate Schematic Recovery Cost
- Sending a single board with no backup. Delamination is sometimes destructive on inner layers. Providing two identical boards lets us preserve one as a continuity-test reference, reducing rework and re-imaging costs.
- Requesting schematic-only when you’ll need Gerber later. Bundling from the start is cheaper because layer imaging is shared across both deliverables.
- Unclear scope. If you only need the power section reverse-engineered for a repair, say so — partial schematic recovery can cut cost by 40–60%.
- Not disclosing board damage. Surprises during delamination add time. Photograph any visible damage before shipping.
When Is Schematic Recovery Worth the Investment?
The most common scenarios our clients face:
- Legacy equipment support — Original manufacturer is defunct or unresponsive, and you need schematics to diagnose field failures or source replacement boards.
- Second-source qualification — You own the design IP but lost the source files, and need to re-create documentation for a new contract manufacturer.
- Failure analysis — A schematic lets your reliability team trace fault paths that board-level inspection alone can’t reveal.
- Product redesign — Migrating a proven analog front-end or power stage into a new platform starts with an accurate schematic of the original.
In every case, the schematic recovery cost is a fraction of a full re-design cycle — typically 5–15% of what a ground-up design of equivalent complexity would run.
Schematic Recovery vs. Related Services: Quick Comparison
| Service | Primary Deliverable | Typical Cost Range | When You Need It |
|---|---|---|---|
| Schematic Recovery | Schematic file + net list | $400 – $6,000+ | Repair, analysis, redesign |
| Gerber Recovery | Gerber / ODB++ fabrication files | $500 – $5,000+ | Board re-fabrication |
| BOM Extraction | Bill of materials with MPN/values | $200 – $1,200 | Procurement, sourcing |
| Full Board Clone | All of the above + assembly data | $1,200 – $10,000+ | Complete replication |
What is the minimum information you need to quote a schematic recovery cost?
We need either the physical board (preferred) or high-resolution photos of both sides plus a note on layer count if known. Board dimensions, the number of BGA/QFN packages, and any known damage help us quote faster. Upload files or photos through our intake form for a preliminary estimate within 1–2 business days.
Can you recover a schematic from a board with potted or conformal-coated components?
Yes, but it adds cost and time. Conformal coating removal runs $100–$300 depending on area and coating type (acrylic vs. silicone vs. urethane). Potted sections may require careful mechanical removal, and there’s a risk of component damage — we’ll flag that risk before proceeding and quote accordingly.
How accurate is a recovered schematic compared to the original design files?
Net connectivity accuracy is typically 99.5%+ after our verification pass. The main limitation is component values for unmarked or custom parts — we document any assumptions and flag parts that need your engineering confirmation. Functional block organization follows standard conventions but may differ from the original designer’s layout choices.
Do you offer partial schematic recovery for just one section of a board?
Absolutely. If you only need the power supply, RF front-end, or a specific interface block, we can scope the project to that area. Partial recovery typically costs 40–60% less than a full-board schematic and ships in roughly half the lead time.
Is my design data kept confidential during schematic recovery?
Every project is covered by our mutual NDA before any work begins. Source boards are stored in a secured facility, and all digital files are encrypted at rest and in transit. We can execute your company’s NDA template if preferred.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewWorking on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
Get a free quote