What Is PCB Stackup Recovery?
PCB stackup recovery is the process of determining every physical layer in a printed circuit board—copper foil weights, prepreg and core thicknesses, dielectric constants, and layer ordering—when original design data is unavailable. Our engineers use micro-sectioning, X-ray imaging, and impedance extraction to rebuild a fabrication-ready stackup drawing that a board house can quote directly. A typical 8-layer FR-4 board takes 3–5 working days; complex 16+ layer HDI designs may need 7–10 days with tighter measurement tolerances of ±0.5 mil on dielectric layers.
Why Does Stackup Recovery Matter?
The stackup defines signal integrity, power delivery, EMC performance, and mechanical fit. If you clone or redesign a board without matching the original stackup, controlled-impedance traces will shift, power-plane resonance will change, and the board may fail EMC testing. Legacy boards from discontinued equipment often have no surviving Gerber or ODB++ data, making stackup recovery the critical first step before rebuilding copper from imaged layers.
Common Scenarios That Trigger Stackup Recovery
- Obsolete equipment support — OEM no longer supplies replacement boards, and no fabrication data exists.
- Second-source qualification — you need to verify a supplier’s stackup matches the approved design.
- Failure analysis — field failures traced to impedance drift require baseline stackup confirmation.
- Cost-reduction redesign — moving to a cheaper laminate system while keeping impedance within spec demands knowing the original structure. Our PCB cost-reduction redesign strategies start here.
How Do Engineers Recover a PCB Stackup?
The workflow below is what our lab follows on every project. Steps 1–3 are destructive; steps 4–6 are analytical.
Step 1 — Visual & X-Ray Pre-Inspection
We photograph both sides under calibrated lighting and run a 2D X-ray scan to count internal layers, locate buried/blind vias, and identify via-in-pad structures. X-ray alone resolves layer count to ±0 layers on boards up to 24 layers.
Step 2 — Micro-Sectioning (Cross-Section Analysis)
A coupon is cut from a non-critical area (typically near a board edge or mounting hole), potted in epoxy, and polished to a mirror finish. Under a metallurgical microscope at 200–500× magnification, we measure each copper layer thickness, prepreg bond-line, and core laminate. Measurement resolution is 0.1 mil (2.5 µm).
Step 3 — Dielectric Identification
We use FTIR (Fourier-Transform Infrared Spectroscopy) or known-laminate comparison tables to identify the resin system—standard FR-4 (Dk ≈ 4.2–4.5 at 1 GHz), mid-loss (Dk ≈ 3.6–3.8), or low-loss PTFE/ceramic-filled (Dk ≈ 3.0–3.5). This matters because impedance scales with √Dk; a 10% Dk error shifts impedance by roughly 5%.
Step 4 — Impedance Extraction
Using TDR (Time-Domain Reflectometry), we probe controlled-impedance traces on the outer layers and, where accessible, inner-layer test coupons. Measured impedance values are cross-referenced against the physical dimensions from Step 2 to validate or adjust the dielectric constant used in the stackup model.
Step 5 — Stackup Modeling & Simulation
We build the stackup in a 2D field solver (Polar Si9000 or equivalent), inputting measured copper weights, dielectric thicknesses, and extracted Dk values. The model is iterated until simulated impedance matches TDR measurements within ±5% or ±2 Ω, whichever is tighter.
Step 6 — Deliverable Generation
The final stackup drawing includes layer order, copper weights (typically 0.5 oz, 1 oz, or 2 oz), prepreg style and ply count, core thickness, finished board thickness, and target impedance values with tolerances. This drawing is part of the broader PCB copy deliverables package alongside Gerber data and a BOM.
Typical Stackup Recovery Specifications
| Parameter | Measurement Method | Typical Tolerance |
|---|---|---|
| Layer count | X-ray + cross-section | Exact (±0) |
| Copper weight per layer | Cross-section micrograph | ±0.1 oz (±3.5 µm) |
| Dielectric thickness | Cross-section micrograph | ±0.5 mil (±12.7 µm) |
| Dk (dielectric constant) | FTIR + TDR correlation | ±0.15 at 1 GHz |
| Controlled impedance (SE/Diff) | TDR measurement | ±5% or ±2 Ω |
| Overall board thickness | Digital micrometer | ±2 mil (±50 µm) |
| Via type identification | X-ray + cross-section | Through / blind / buried / µvia |
BGA Fanout and Its Role in Stackup Recovery
High-pin-count BGAs often dictate the minimum layer count and via technology in a stackup. A 0.8 mm pitch BGA with 400+ balls typically requires at least two routing layers with dog-bone vias or via-in-pad structures, which in turn demand specific prepreg thicknesses and laser-drillable dielectric layers. During stackup recovery, identifying the BGA escape strategy tells us whether the board uses sequential lamination (HDI) or conventional through-hole construction.
Use the planner below to check how many routing layers a given BGA pitch and pin count requires—then compare that against the recovered layer count to validate the stackup model.
PCB design
BGA Fanout and Escape Routing Planner
How many rows escape per layer, and whether you can avoid via-in-pad. Decide this at schematic time, when the package is still a free choice.
How this is calculated
The arithmetic is simple: subtract the pad diameter from the pitch to get the copper-free gap, then see how many trace-plus-space channels fit in it. Each channel clears roughly one more row of balls per internal layer, plus the two outer rows that escape on the surface.
The result decides your layer count and often your entire fabrication class. At 0.8 mm pitch you can dog-bone out with standard vias. At 0.5 mm the via land no longer fits between pads and you need via-in-pad, which means filled and capped vias. At 0.4 mm you are building an HDI board with microvias whether that was the plan or not.
If the planner indicates four escape layers but cross-sectioning reveals only two signal layers under the BGA, that flags a via-in-pad or stacked-microvia design that changes the stackup assumptions significantly. Our BGA escape routing and pad recovery guide covers these cases in detail.
What Can Go Wrong During Stackup Recovery?
Stackup recovery is not always straightforward. Here are failure modes we encounter and how we handle them.
Damaged or Corroded Cross-Section Coupons
Boards exposed to moisture, heat, or chemical contamination may have delaminated prepreg or corroded copper. This makes thickness measurements unreliable. We take multiple coupons from different board areas and average the results, discarding outliers.
Non-Standard or Custom Laminates
Some OEMs use proprietary laminate blends or hybrid stackups (e.g., Rogers core with FR-4 prepreg). FTIR can narrow the resin family but may not pinpoint the exact product code. In these cases, we model the stackup with the closest commercially available equivalent and note the substitution in the deliverable.
Asymmetric Stackups
Boards designed with intentionally asymmetric layer spacing—common in military-spec obsolescence recovery projects—require careful measurement of every individual dielectric layer rather than assuming symmetry. Missing this detail causes warpage in the reproduced board.
Flex and Rigid-Flex Constructions
Polyimide cores, adhesive layers, and coverlay films add complexity. Dielectric constants differ from FR-4 (polyimide Dk ≈ 3.2–3.5), and bend-area stackups may omit copper layers entirely. Our flex PCB recovery workflow addresses these unique challenges.
Stackup Recovery Checklist for Engineers
Before sending a board for stackup recovery, prepare the following to accelerate turnaround:
- At least one complete, undamaged sample board (two preferred for destructive testing).
- Any partial documentation—schematics, impedance specs, or fabrication notes—even handwritten.
- Known operating frequencies or data rates for impedance-critical nets.
- Target application context (consumer, industrial, automotive, mil-aero) so we apply the right IPC class assumptions (Class 2 vs. Class 3).
- Photographs of both sides and any visible layer edges—see what board photographs can reveal before physical analysis begins.
Turnaround and Pricing Signals
Stackup recovery is typically bundled into a full PCB reverse engineering engagement, but it can be ordered as a standalone service for failure analysis or supplier qualification.
| Board Complexity | Layer Count | Typical Turnaround | Starting Price Range |
|---|---|---|---|
| Simple | 2–4 layers, FR-4 | 2–3 working days | $200–$400 |
| Moderate | 6–10 layers, standard HDI | 3–5 working days | $400–$900 |
| Complex | 12–20+ layers, mixed dielectrics | 7–10 working days | $900–$2,000+ |
Prices depend on via technology (through-hole vs. sequential lamination), laminate exoticism, and whether TDR impedance verification is required. We provide a binding quote within 24 hours of receiving the board.
Check feasibility for your project
Send the chip marking or board details and tell us what you need to recover. Add clear photos if available.
Request a feasibility reviewCan you recover a stackup without destroying the board?
Partially. X-ray imaging and TDR probing are non-destructive and can determine layer count, via types, and impedance. However, precise dielectric thickness and copper weight measurements require micro-sectioning, which destroys a small coupon area (typically 10 × 15 mm). If only one board exists, we section from the least critical edge and document the trade-off before cutting.
How accurate is recovered impedance compared to the original design?
Our validated stackup models match TDR-measured impedance within ±5% or ±2 Ω. For most digital designs (USB, HDMI, DDR), this is within the IPC-2141 recommended fabrication tolerance. RF designs above 6 GHz may need additional dielectric characterization to tighten the Dk accuracy beyond our standard ±0.15 resolution.
What if the board uses buried or stacked microvias?
Sequential-lamination boards with stacked or staggered microvias require multiple cross-section cuts at different locations to map the full via structure. X-ray gives us the via map; cross-sections confirm drill diameters (typically 75–150 µm for laser vias) and capture pad dimensions. This adds 1–2 days to the standard turnaround.
Do you recover the stackup for aluminum-core or metal-substrate boards?
Yes. Aluminum and copper-core boards have a unique thermal-interface dielectric layer (often 75–150 µm thermally conductive prepreg). We measure the metal core thickness, dielectric layer, and top copper separately. See our aluminum board reconstruction guide for specifics.
Is stackup recovery enough to reproduce the board, or do I need full reverse engineering?
Stackup recovery alone gives you the layer structure and impedance targets—enough for failure analysis or supplier audits. To actually reproduce the board, you also need Gerber files (copper artwork for every layer), drill data, and a BOM. Most clients pair stackup recovery with our complete board-level reverse engineering to get a fabrication-ready package.
Working on a board like this?
Send the chip marking or two photos. You get feasibility, lead time and price within 24 hours, and the check costs nothing.
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